A wide range of electronic circuits and devices, such as cellular phones, GPS devices, and other systems, require the presence of a continuous clock signal with a constant clock frequency. A clock frequency generating unit should be able to automatically correct frequency drifts in a generated clock frequency without producing an intolerable frequency error, at all times, including the time at which corrections are performed.
One widely used approach for generating a self-correcting clock frequency includes use of a phase-locked loop. One of the components in the phase-locked loop is the voltage controlled oscillator (VCO). However, a VCO oscillating frequency exhibits a dependence on temperature or other environmental stress, which causes the frequency of a signal generated by a VCO to drift in accordance with changes in the VCO's operational temperature, or other environmental stresses.
However, because the VCO in a phase-locked loop is enclosed in a feedback loop in which the VCO frequency is locked to a stable reference clock frequency, the VCO frequency can be adjusted by the control loop, automatically, and compensate for the frequency drift of the VCO as long as the loop response time is shorter than the rate of temperature change or other environmental changes and the frequency drift is within the VCO's correctable range.
The frequency of a signal generated by a VCO in response to an input control voltage can be adjusted by changing the capacitance value of an inductance/capacitance (LC) tank circuit included in the VCO. The value of the capacitance can be changed by either adjusting the value of a varactor, or by adjusting the number of discrete capacitor bank units connecting to the tank circuit. In the case where the frequency is adjusted through a continuously tunable varactor, the range of VCO frequency that such compensation can achieve is limited by the Kvco, i.e., the sensitivity of VCO frequency change to control signal change, and the range of the control signal. The control signal range is limited by the supply voltage and other components in the PLL. As operating supply voltage decreases, its control signal range reduces.
In order to cover the expected frequency drift of the VCO over an expected operational temperature range, the Kvco may be increased. However, increasing the Kvco constrains the minimum value of the Kvco, adversely affects the phase noise performance and indirectly affects other performance metrics of the PLL. In cases in which the frequency is adjusted by switching in or out discrete units of capacitance, an instantaneous jump in frequency will occur and this will create an instantaneous frequency error that will be corrected by the PLL over time. However, the relative large frequency jump at the beginning of the capacitance adjustment is typically too large for practical implementation and is proven to be unacceptable by most applications.
Hence, a need exists for a phase-locked loop that supports a large frequency drift capability, yet maintains a low Kvco, and does not introduce noise or discontinuities in the frequency of the generated phase-locked loop output signal.